\doxysection{ADC\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_a_d_c___type_def}{}\label{struct_a_d_c___type_def}\index{ADC\_TypeDef@{ADC\_TypeDef}}


Analog to Digital Converter.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_add06351bbb4cf771125247d62b145d75}{ISR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a78d24b9deed83e90a2ff96c95ba94934}{IER}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a6126350919b341bfb13c0b24b30dc22a}{CR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a40a83116e2176d7197fc4b7d0eb08609}{CFGR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a0a4c0d337b0e546e549678b77ea63246}{CFGR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a73009a8122fcc628f467a4e997109347}{SMPR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a9e68fe36c4c8fbbac294b5496ccf7130}{SMPR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_ac73ab76ad0855b2f4b49df96ab954516}{PCSEL\+\_\+\+RES0}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_af1d4e31442e2cdebc1f76b78b095a8ae}{LTR1\+\_\+\+TR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a012000126b1fd446887857938a6c4614}{HTR1\+\_\+\+TR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a47e3166ad06d5f41064a5b7b28d59962}{RES1\+\_\+\+TR3}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a30aca300e6a05f1afa16406770c0dd52}{RESERVED2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a0185aa54962ba987f192154fb7a2d673}{SQR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a6b6e55e6c667042e5a46a76518b73d5a}{SQR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a51dbdba74c4d3559157392109af68fc6}{SQR3}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_ab66c9816c1ca151a6ec728ec55655264}{SQR4}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a84114accead82bd11a0e12a429cdfed9}{DR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_ad4ffd02fea1594fdd917132e217e466a}{RESERVED3}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a09db4799beea24a29003049cd0c37c0f}{RESERVED4}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a5438a76a93ac1bd2526e92ef298dc193}{JSQR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a493d06dfdd25a614290df54467a78348}{RESERVED5}} \mbox{[}4\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a97988c41c381690e8a38fec8d2d24ca5}{OFR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_ae446fdae782b6dd059e348fc877681a6}{OFR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a23083f97baee16e0002366547c8cb5ea}{OFR3}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a232fcdf46374a9c267c2a6533a777fac}{OFR4}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a88e899f86a7e3c7af30d561c59673812}{RESERVED6}} \mbox{[}4\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_ab4b0a79a9e4a9d5b0a24d7285cf55bdc}{JDR1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a898b87cab4f099bcca981cc4c9318b51}{JDR2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a40999cd0a255ef62b2340e2726695063}{JDR3}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_abae6e9d688b16ef350878998f5e21c0b}{JDR4}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a5bc7bf8bf72fa68fa6fe17e3f70ed892}{RESERVED7}} \mbox{[}4\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a02a34c693903ef6ac7326ed02582fdcf}{AWD2\+CR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a3be9b42a9cf52d1b6776c2cfa439592f}{AWD3\+CR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a0ba5631f55ff82a9a375d4b0e6b63467}{RESERVED8}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a35454801a099515a661b1fee41e4736b}{RESERVED9}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_ac330f007ceb75f385a62443e8ddd9c0d}{LTR2\+\_\+\+DIFSEL}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a7de1ecd49b58ac466fda27aef6e63e52}{HTR2\+\_\+\+CALFACT}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a8efc5085ede3544de60dce2979fff160}{LTR3\+\_\+\+RES10}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_aeffc64da996c494b9eaf92fb31e66a61}{HTR3\+\_\+\+RES11}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_a91cccc0d0a05c3c9e0a76efffa423793}{DIFSEL\+\_\+\+RES12}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_acb8f02ad1b8f9e65955fc11f47ef2e4b}{CALFACT\+\_\+\+RES13}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_a_d_c___type_def_ae2a9ddff6ae4c52a011f8f5fa15d8b57}{CALFACT2\+\_\+\+RES14}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Analog to Digital Converter. 

\label{doc-variable-members}
\Hypertarget{struct_a_d_c___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_a_d_c___type_def_a02a34c693903ef6ac7326ed02582fdcf}\index{ADC\_TypeDef@{ADC\_TypeDef}!AWD2CR@{AWD2CR}}
\index{AWD2CR@{AWD2CR}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{AWD2CR}{AWD2CR}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a02a34c693903ef6ac7326ed02582fdcf} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+AWD2\+CR}

ADC Analog Watchdog 2 Configuration Register, Address offset\+: 0x\+A0 \Hypertarget{struct_a_d_c___type_def_a3be9b42a9cf52d1b6776c2cfa439592f}\index{ADC\_TypeDef@{ADC\_TypeDef}!AWD3CR@{AWD3CR}}
\index{AWD3CR@{AWD3CR}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{AWD3CR}{AWD3CR}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a3be9b42a9cf52d1b6776c2cfa439592f} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+AWD3\+CR}

ADC Analog Watchdog 3 Configuration Register, Address offset\+: 0x\+A4 \Hypertarget{struct_a_d_c___type_def_ae2a9ddff6ae4c52a011f8f5fa15d8b57}\index{ADC\_TypeDef@{ADC\_TypeDef}!CALFACT2\_RES14@{CALFACT2\_RES14}}
\index{CALFACT2\_RES14@{CALFACT2\_RES14}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CALFACT2\_RES14}{CALFACT2\_RES14}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_ae2a9ddff6ae4c52a011f8f5fa15d8b57} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+CALFACT2\+\_\+\+RES14}

ADC Linearity Calibration Factors specific ADC1/2, Address offset\+: 0x\+C8 \Hypertarget{struct_a_d_c___type_def_acb8f02ad1b8f9e65955fc11f47ef2e4b}\index{ADC\_TypeDef@{ADC\_TypeDef}!CALFACT\_RES13@{CALFACT\_RES13}}
\index{CALFACT\_RES13@{CALFACT\_RES13}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CALFACT\_RES13}{CALFACT\_RES13}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_acb8f02ad1b8f9e65955fc11f47ef2e4b} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+CALFACT\+\_\+\+RES13}

ADC Calibration Factors specific ADC1/2, Address offset\+: 0x\+C4 \Hypertarget{struct_a_d_c___type_def_a40a83116e2176d7197fc4b7d0eb08609}\index{ADC\_TypeDef@{ADC\_TypeDef}!CFGR@{CFGR}}
\index{CFGR@{CFGR}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CFGR}{CFGR}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a40a83116e2176d7197fc4b7d0eb08609} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+CFGR}

ADC Configuration register, Address offset\+: 0x0C \Hypertarget{struct_a_d_c___type_def_a0a4c0d337b0e546e549678b77ea63246}\index{ADC\_TypeDef@{ADC\_TypeDef}!CFGR2@{CFGR2}}
\index{CFGR2@{CFGR2}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CFGR2}{CFGR2}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a0a4c0d337b0e546e549678b77ea63246} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+CFGR2}

ADC Configuration register 2, Address offset\+: 0x10 \Hypertarget{struct_a_d_c___type_def_a6126350919b341bfb13c0b24b30dc22a}\index{ADC\_TypeDef@{ADC\_TypeDef}!CR@{CR}}
\index{CR@{CR}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR}{CR}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a6126350919b341bfb13c0b24b30dc22a} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+CR}

ADC control register, Address offset\+: 0x08 \Hypertarget{struct_a_d_c___type_def_a91cccc0d0a05c3c9e0a76efffa423793}\index{ADC\_TypeDef@{ADC\_TypeDef}!DIFSEL\_RES12@{DIFSEL\_RES12}}
\index{DIFSEL\_RES12@{DIFSEL\_RES12}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DIFSEL\_RES12}{DIFSEL\_RES12}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a91cccc0d0a05c3c9e0a76efffa423793} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+DIFSEL\+\_\+\+RES12}

ADC Differential Mode Selection Register specific ADC1/2, Address offset\+: 0x\+C0 \Hypertarget{struct_a_d_c___type_def_a84114accead82bd11a0e12a429cdfed9}\index{ADC\_TypeDef@{ADC\_TypeDef}!DR@{DR}}
\index{DR@{DR}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DR}{DR}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a84114accead82bd11a0e12a429cdfed9} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+DR}

ADC regular data register, Address offset\+: 0x40 \Hypertarget{struct_a_d_c___type_def_a012000126b1fd446887857938a6c4614}\index{ADC\_TypeDef@{ADC\_TypeDef}!HTR1\_TR2@{HTR1\_TR2}}
\index{HTR1\_TR2@{HTR1\_TR2}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{HTR1\_TR2}{HTR1\_TR2}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a012000126b1fd446887857938a6c4614} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+HTR1\+\_\+\+TR2}

ADC watchdog higher threshold register 1, Address offset\+: 0x24 \Hypertarget{struct_a_d_c___type_def_a7de1ecd49b58ac466fda27aef6e63e52}\index{ADC\_TypeDef@{ADC\_TypeDef}!HTR2\_CALFACT@{HTR2\_CALFACT}}
\index{HTR2\_CALFACT@{HTR2\_CALFACT}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{HTR2\_CALFACT}{HTR2\_CALFACT}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a7de1ecd49b58ac466fda27aef6e63e52} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+HTR2\+\_\+\+CALFACT}

ADC watchdog Higher threshold register 2, Calfact for ADC3, Address offset\+: 0x\+B4 \Hypertarget{struct_a_d_c___type_def_aeffc64da996c494b9eaf92fb31e66a61}\index{ADC\_TypeDef@{ADC\_TypeDef}!HTR3\_RES11@{HTR3\_RES11}}
\index{HTR3\_RES11@{HTR3\_RES11}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{HTR3\_RES11}{HTR3\_RES11}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_aeffc64da996c494b9eaf92fb31e66a61} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+HTR3\+\_\+\+RES11}

ADC watchdog Higher threshold register 3, specific ADC1/2, Address offset\+: 0x\+BC \Hypertarget{struct_a_d_c___type_def_a78d24b9deed83e90a2ff96c95ba94934}\index{ADC\_TypeDef@{ADC\_TypeDef}!IER@{IER}}
\index{IER@{IER}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IER}{IER}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a78d24b9deed83e90a2ff96c95ba94934} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+IER}

ADC Interrupt Enable Register, Address offset\+: 0x04 \Hypertarget{struct_a_d_c___type_def_add06351bbb4cf771125247d62b145d75}\index{ADC\_TypeDef@{ADC\_TypeDef}!ISR@{ISR}}
\index{ISR@{ISR}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ISR}{ISR}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_add06351bbb4cf771125247d62b145d75} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+ISR}

ADC Interrupt and Status Register, Address offset\+: 0x00 \Hypertarget{struct_a_d_c___type_def_ab4b0a79a9e4a9d5b0a24d7285cf55bdc}\index{ADC\_TypeDef@{ADC\_TypeDef}!JDR1@{JDR1}}
\index{JDR1@{JDR1}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{JDR1}{JDR1}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_ab4b0a79a9e4a9d5b0a24d7285cf55bdc} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+JDR1}

ADC injected data register 1, Address offset\+: 0x80 \Hypertarget{struct_a_d_c___type_def_a898b87cab4f099bcca981cc4c9318b51}\index{ADC\_TypeDef@{ADC\_TypeDef}!JDR2@{JDR2}}
\index{JDR2@{JDR2}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{JDR2}{JDR2}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a898b87cab4f099bcca981cc4c9318b51} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+JDR2}

ADC injected data register 2, Address offset\+: 0x84 \Hypertarget{struct_a_d_c___type_def_a40999cd0a255ef62b2340e2726695063}\index{ADC\_TypeDef@{ADC\_TypeDef}!JDR3@{JDR3}}
\index{JDR3@{JDR3}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{JDR3}{JDR3}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a40999cd0a255ef62b2340e2726695063} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+JDR3}

ADC injected data register 3, Address offset\+: 0x88 \Hypertarget{struct_a_d_c___type_def_abae6e9d688b16ef350878998f5e21c0b}\index{ADC\_TypeDef@{ADC\_TypeDef}!JDR4@{JDR4}}
\index{JDR4@{JDR4}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{JDR4}{JDR4}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_abae6e9d688b16ef350878998f5e21c0b} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+JDR4}

ADC injected data register 4, Address offset\+: 0x8C \Hypertarget{struct_a_d_c___type_def_a5438a76a93ac1bd2526e92ef298dc193}\index{ADC\_TypeDef@{ADC\_TypeDef}!JSQR@{JSQR}}
\index{JSQR@{JSQR}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{JSQR}{JSQR}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a5438a76a93ac1bd2526e92ef298dc193} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+JSQR}

ADC injected sequence register, Address offset\+: 0x4C \Hypertarget{struct_a_d_c___type_def_af1d4e31442e2cdebc1f76b78b095a8ae}\index{ADC\_TypeDef@{ADC\_TypeDef}!LTR1\_TR1@{LTR1\_TR1}}
\index{LTR1\_TR1@{LTR1\_TR1}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{LTR1\_TR1}{LTR1\_TR1}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_af1d4e31442e2cdebc1f76b78b095a8ae} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+LTR1\+\_\+\+TR1}

ADC watchdog Lower threshold register 1, Address offset\+: 0x20 \Hypertarget{struct_a_d_c___type_def_ac330f007ceb75f385a62443e8ddd9c0d}\index{ADC\_TypeDef@{ADC\_TypeDef}!LTR2\_DIFSEL@{LTR2\_DIFSEL}}
\index{LTR2\_DIFSEL@{LTR2\_DIFSEL}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{LTR2\_DIFSEL}{LTR2\_DIFSEL}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_ac330f007ceb75f385a62443e8ddd9c0d} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+LTR2\+\_\+\+DIFSEL}

ADC watchdog Lower threshold register 2, Difsel for ADC3, Address offset\+: 0x\+B0 \Hypertarget{struct_a_d_c___type_def_a8efc5085ede3544de60dce2979fff160}\index{ADC\_TypeDef@{ADC\_TypeDef}!LTR3\_RES10@{LTR3\_RES10}}
\index{LTR3\_RES10@{LTR3\_RES10}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{LTR3\_RES10}{LTR3\_RES10}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a8efc5085ede3544de60dce2979fff160} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+LTR3\+\_\+\+RES10}

ADC watchdog Lower threshold register 3, specific ADC1/2, Address offset\+: 0x\+B8 \Hypertarget{struct_a_d_c___type_def_a97988c41c381690e8a38fec8d2d24ca5}\index{ADC\_TypeDef@{ADC\_TypeDef}!OFR1@{OFR1}}
\index{OFR1@{OFR1}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{OFR1}{OFR1}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a97988c41c381690e8a38fec8d2d24ca5} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+OFR1}

ADC offset register 1, Address offset\+: 0x60 \Hypertarget{struct_a_d_c___type_def_ae446fdae782b6dd059e348fc877681a6}\index{ADC\_TypeDef@{ADC\_TypeDef}!OFR2@{OFR2}}
\index{OFR2@{OFR2}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{OFR2}{OFR2}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_ae446fdae782b6dd059e348fc877681a6} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+OFR2}

ADC offset register 2, Address offset\+: 0x64 \Hypertarget{struct_a_d_c___type_def_a23083f97baee16e0002366547c8cb5ea}\index{ADC\_TypeDef@{ADC\_TypeDef}!OFR3@{OFR3}}
\index{OFR3@{OFR3}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{OFR3}{OFR3}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a23083f97baee16e0002366547c8cb5ea} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+OFR3}

ADC offset register 3, Address offset\+: 0x68 \Hypertarget{struct_a_d_c___type_def_a232fcdf46374a9c267c2a6533a777fac}\index{ADC\_TypeDef@{ADC\_TypeDef}!OFR4@{OFR4}}
\index{OFR4@{OFR4}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{OFR4}{OFR4}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a232fcdf46374a9c267c2a6533a777fac} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+OFR4}

ADC offset register 4, Address offset\+: 0x6C \Hypertarget{struct_a_d_c___type_def_ac73ab76ad0855b2f4b49df96ab954516}\index{ADC\_TypeDef@{ADC\_TypeDef}!PCSEL\_RES0@{PCSEL\_RES0}}
\index{PCSEL\_RES0@{PCSEL\_RES0}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PCSEL\_RES0}{PCSEL\_RES0}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_ac73ab76ad0855b2f4b49df96ab954516} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+PCSEL\+\_\+\+RES0}

Reserved for ADC3, ADC1/2 pre-\/channel selection, Address offset\+: 0x1C \Hypertarget{struct_a_d_c___type_def_a47e3166ad06d5f41064a5b7b28d59962}\index{ADC\_TypeDef@{ADC\_TypeDef}!RES1\_TR3@{RES1\_TR3}}
\index{RES1\_TR3@{RES1\_TR3}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RES1\_TR3}{RES1\_TR3}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a47e3166ad06d5f41064a5b7b28d59962} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+RES1\+\_\+\+TR3}

Reserved for ADC1/2, ADC3 threshold register, Address offset\+: 0x28 \Hypertarget{struct_a_d_c___type_def_a30aca300e6a05f1afa16406770c0dd52}\index{ADC\_TypeDef@{ADC\_TypeDef}!RESERVED2@{RESERVED2}}
\index{RESERVED2@{RESERVED2}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED2}{RESERVED2}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a30aca300e6a05f1afa16406770c0dd52} 
uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+RESERVED2}

Reserved, 0x02C \Hypertarget{struct_a_d_c___type_def_ad4ffd02fea1594fdd917132e217e466a}\index{ADC\_TypeDef@{ADC\_TypeDef}!RESERVED3@{RESERVED3}}
\index{RESERVED3@{RESERVED3}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED3}{RESERVED3}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_ad4ffd02fea1594fdd917132e217e466a} 
uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+RESERVED3}

Reserved, 0x044 \Hypertarget{struct_a_d_c___type_def_a09db4799beea24a29003049cd0c37c0f}\index{ADC\_TypeDef@{ADC\_TypeDef}!RESERVED4@{RESERVED4}}
\index{RESERVED4@{RESERVED4}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED4}{RESERVED4}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a09db4799beea24a29003049cd0c37c0f} 
uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+RESERVED4}

Reserved, 0x048 \Hypertarget{struct_a_d_c___type_def_a493d06dfdd25a614290df54467a78348}\index{ADC\_TypeDef@{ADC\_TypeDef}!RESERVED5@{RESERVED5}}
\index{RESERVED5@{RESERVED5}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED5}{RESERVED5}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a493d06dfdd25a614290df54467a78348} 
uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+RESERVED5\mbox{[}4\mbox{]}}

Reserved, 0x050 -\/ 0x05C \Hypertarget{struct_a_d_c___type_def_a88e899f86a7e3c7af30d561c59673812}\index{ADC\_TypeDef@{ADC\_TypeDef}!RESERVED6@{RESERVED6}}
\index{RESERVED6@{RESERVED6}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED6}{RESERVED6}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a88e899f86a7e3c7af30d561c59673812} 
uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+RESERVED6\mbox{[}4\mbox{]}}

Reserved, 0x070 -\/ 0x07C \Hypertarget{struct_a_d_c___type_def_a5bc7bf8bf72fa68fa6fe17e3f70ed892}\index{ADC\_TypeDef@{ADC\_TypeDef}!RESERVED7@{RESERVED7}}
\index{RESERVED7@{RESERVED7}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED7}{RESERVED7}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a5bc7bf8bf72fa68fa6fe17e3f70ed892} 
uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+RESERVED7\mbox{[}4\mbox{]}}

Reserved, 0x090 -\/ 0x09C \Hypertarget{struct_a_d_c___type_def_a0ba5631f55ff82a9a375d4b0e6b63467}\index{ADC\_TypeDef@{ADC\_TypeDef}!RESERVED8@{RESERVED8}}
\index{RESERVED8@{RESERVED8}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED8}{RESERVED8}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a0ba5631f55ff82a9a375d4b0e6b63467} 
uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+RESERVED8}

Reserved, 0x0\+A8 \Hypertarget{struct_a_d_c___type_def_a35454801a099515a661b1fee41e4736b}\index{ADC\_TypeDef@{ADC\_TypeDef}!RESERVED9@{RESERVED9}}
\index{RESERVED9@{RESERVED9}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED9}{RESERVED9}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a35454801a099515a661b1fee41e4736b} 
uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+RESERVED9}

Reserved, 0x0\+AC \Hypertarget{struct_a_d_c___type_def_a73009a8122fcc628f467a4e997109347}\index{ADC\_TypeDef@{ADC\_TypeDef}!SMPR1@{SMPR1}}
\index{SMPR1@{SMPR1}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SMPR1}{SMPR1}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a73009a8122fcc628f467a4e997109347} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+SMPR1}

ADC sample time register 1, Address offset\+: 0x14 \Hypertarget{struct_a_d_c___type_def_a9e68fe36c4c8fbbac294b5496ccf7130}\index{ADC\_TypeDef@{ADC\_TypeDef}!SMPR2@{SMPR2}}
\index{SMPR2@{SMPR2}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SMPR2}{SMPR2}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a9e68fe36c4c8fbbac294b5496ccf7130} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+SMPR2}

ADC sample time register 2, Address offset\+: 0x18 \Hypertarget{struct_a_d_c___type_def_a0185aa54962ba987f192154fb7a2d673}\index{ADC\_TypeDef@{ADC\_TypeDef}!SQR1@{SQR1}}
\index{SQR1@{SQR1}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SQR1}{SQR1}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a0185aa54962ba987f192154fb7a2d673} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+SQR1}

ADC regular sequence register 1, Address offset\+: 0x30 \Hypertarget{struct_a_d_c___type_def_a6b6e55e6c667042e5a46a76518b73d5a}\index{ADC\_TypeDef@{ADC\_TypeDef}!SQR2@{SQR2}}
\index{SQR2@{SQR2}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SQR2}{SQR2}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a6b6e55e6c667042e5a46a76518b73d5a} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+SQR2}

ADC regular sequence register 2, Address offset\+: 0x34 \Hypertarget{struct_a_d_c___type_def_a51dbdba74c4d3559157392109af68fc6}\index{ADC\_TypeDef@{ADC\_TypeDef}!SQR3@{SQR3}}
\index{SQR3@{SQR3}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SQR3}{SQR3}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_a51dbdba74c4d3559157392109af68fc6} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+SQR3}

ADC regular sequence register 3, Address offset\+: 0x38 \Hypertarget{struct_a_d_c___type_def_ab66c9816c1ca151a6ec728ec55655264}\index{ADC\_TypeDef@{ADC\_TypeDef}!SQR4@{SQR4}}
\index{SQR4@{SQR4}!ADC\_TypeDef@{ADC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SQR4}{SQR4}}
{\footnotesize\ttfamily \label{struct_a_d_c___type_def_ab66c9816c1ca151a6ec728ec55655264} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t ADC\+\_\+\+Type\+Def\+::\+SQR4}

ADC regular sequence register 4, Address offset\+: 0x3C 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
